You may know make as a tool for building software, but it's actually a general utility for performing tasks based on a dependency graph, even if those tasks have nothing to do with compiling software. In many situations, files are processed in some way to create other files or perform certain tasks. For example:
- A .c file is compiled to make a .o file, which is then linked to other object files to make an executable.
- A .tex file is processed by LaTeX to make a PDF file.
- A file containing data is processed by a script to generate graphs.
- A web page needs to be uploaded to a remote server after it is modified.
- A piece of software needs to be installed after it is compiled.
make automates the process of keeping resources up-to-date: you tell it about what resources depend on what source files, and what needs to be done to those source files to make the resources. It then runs only those tasks that actually need to be run. No more obsessive-compulsive internal dialogues that go like this: "Did I remember to compile that program again after I was done changing it?" "Well, I don't remember, so I might as well do it again." Running a properly-configured make will compile your program if it's necessary, and do nothing if your program is up-to-date. This can save you seconds, minutes, or hours, depending on what you're doing.
make determines what to do by comparing the modification times of the resources and the source files. For example, if thesis.pdf (a resource) is created from thesis.tex (a source file), then pdflatex needs to be run if thesis.pdf doesn't exist or if it's older than thesis.tex, but nothing needs to be done if thesis.pdf is newer than thesis.tex.
To use make to manage some files in a directory, create a file called Makefile in that directory. The syntax for the Makefile is refreshingly simple. For each resource to generate (these are called targets), type:
TARGET-FILE: DEPENDENCY-FILE-1 DEPENDENCY-FILE-2 ...
COMMAND-TO-RUN
ANOTHER-COMMAND
Each command to be run should be indented with a single tab. Here's an example Makefile, for a system where two files are to be compiled, then linked to make an executable:
helloworld: hello1.o hello2.o
gcc -o helloworld hello1.o hello2.o
hello1.o: hello1.c
gcc -c hello1.c
hello2.o: hello2.c
gcc -c hello2.c
Running $ make helloworld tells make to resolve the dependencies necessary to generate the file helloworld: make first compiles the two source files, then links them. If I were to subsequently change hello1.c and run $ make helloworld again, make would recompile that file and relink the program, but it would not recompile hello2.c.
By default, $ make (without a target name) does whatever is necessary to make the first target that appears in your Makefile (in this case, helloworld).
In fact, your make targets do not have to refer to files. You can use make to define groups of commands to be run together under an (arbitrary) easy-to-remember target name. For example, I could define a publish target which would upload my web pages:
.PHONY: publish
publish: index.html stuff.html
scp index.html stuff.html phil@remoteserver:~/www/
(The .PHONY directive tells make to not worry that a file named publish is not being generated.) Now publishing my web page is as easy as running $ make publish.
Here are some common applications of phony targets:
- After you compile a piece of software, you can frequently install it with $ make install.
- $ make clean usually has the job of removing compiled files from a directory (so you are left with the "clean" source files). It can often be defined similarly to this:
.PHONY: clean clean: rm -f helloworld *.o - If a source directory contains multiple independent targets, an all target is usually created to force building the individual parts, and placed first so that $ make invokes $ make all:
.PHONY: all all: part1 part2 part3
As you can see, you can use make to automate any well-defined process you're going to want to do repeatedly.
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